1. Field of the Invention
The present invention relates to a differential RS latch circuit for use in a semiconductor integrated circuit such as an ECL (emitter-coupled logic) gate array for use in a high-speed digital circuit, and more particular to a differential RS latch circuit which causes no output hazard.
2. Description of the Related Art
In general, an RS latch circuit operates according to the following truth table:
______________________________________ Reset input R "0" "1" "0" "1" Set input S "0" "0" "1" "1" Output Qn Qn - 1 "0" "1" ".o slashed." ______________________________________
When R=S="0", the output Qn-1 is generated before the output Qn. The output ".phi." generated when R=S="1" (prohibited output) is either "0" or "1". A circuit which outputs "0" (".phi."="0") is called first-to-reset type RS latch circuit, and a circuit which outputs "1" (".phi."="1") is called first-to-set type RS latch circuit.
The operation of the first-to-reset type RS latch circuit is given by the following logical expression: ##EQU1##
The operation of the first-to-set type RS latch circuit is given by the logical expression: ##EQU2##
FIG. 1 is a logic circuit diagram showing the first-to-reset RS latch circuit constituted by NOR gates 41 and 42.
FIG. 2 is a circuit diagram showing a conventional differential RS latch circuit having an ECL gate. The conventional differential RS circuit of FIG. 2 is designed to effect a differential logic function, on the basis of the RS latch circuit of FIG. 1.
In FIG. 5, Q51 to Q76 denote NPN transistors, and R51 to R54 and R67 to R76 denote resistances. The transistors Q51 and Q52, transistors Q53 and Q54, transistors Q55 and Q56, and transistors Q57 and Q58 are differential pairs, respectively. The transistors Q59 to Q66 are parts of emitter follower circuits, and the transistors Q67 to Q76 are parts of current source circuits, respectively. A bias voltage Vcc is applied to the base of each of the transistors Q67 to Q76.
The structure and operation of the above differential RS latch circuit are well known, and will be explained but briefly.
In the differential RS latch circuit, a signal is delayed by time ts as it is transmitted from a set input S node to an output Qn node. The delay time ts is twice as much as the time tr by which a signal is delayed as is transmitted from a reset input R node to the output Qn node. The response speed to set input at which the set input is processed in the RS latch circuit differs from that for reset input at which the reset input is processed in the RS latch circuit.
If each of the currents flowing through current source circuits shown in FIG. 2 has a value Io, their total value is 10.times.Io. The total consumption of the currents is large.
As is clear from the above, the conventional differential RS latch circuit has problems. First, the response speed at which the set input is processed in the RS latch circuit differs from that at which the reset input is processed in the RS latch circuit. Second, a large number of current source circuits are required. Third, the current consumption is large. In addition, a transient erroneous operation (hazard) occurs at the time of a switching operation, e.g., the time when one current path is switched to another.